1. Field of the Invention
The present invention relates generally to wafer carriers. More particularly, the present invention relates to systems for ensuring such carriers are suitable for use.
2. Description of Related Art
Wafer carriers have been used for many years in the electronic arts, particularly the semiconductor arts, to support wafers during processing. Typical wafer carriers are described, for example, in U.S. Pat. Nos. 4,993,559; 4,355,974; 4,256,229; 4,515,104; 3,678,893; 3,534,862; 4,023,691; and 3,610,613, which are all incorporated herein by reference. Quartz is a common construction material for wafer carriers that are intended for use in high temperature processes. Other materials are also used.
The processing of wafers to make integrated circuit chips requires that they be successively immersed, sprayed and/or rinsed with liquids or gases. Some of the chemical baths include corrosive chemicals. Some involve very high temperatures. One such process that is frequently employed is chemical vapor deposition ("CVD"). CVD involves depositing a solid material from a gaseous phase onto a substrate by means of a chemical reaction. This deposition reaction is generally thermal decomposition, chemical oxidation, or chemical reduction. Chemical vapor deposition of electronic materials is described by T. L. Chu et al., J. Vac. Sci. Technol. 10: 1 (1973) and B. E. Watts, Thin Solid Films. 18: 1 (1973). They describe the formation and doping of epitaxial films of such materials as silicon, germanium and GaAs. A summary of the chemical vapor deposition field is provided by W. A. Bryant, "The Fundamentals of Chemical Vapour Deposition", Journal of Materials Science. 12: 1285 (1977). Low pressure CVD production of silicon dioxide deposits is summarized by R. Rossler, Solid State Technology, 63-70 (April 1977). The contents of each of the foregoing are incorporated herein by reference.
The positioning of a plurality of wafers in a row in a vapor deposition device has been previously described in U.S. Pat. No. 3,471,326, and placing them in a vertical orientation has been described in U.S. Pat. Nos. 3,922,467 and 4,018,183.
In CVD furnaces, spacing between wafers when disposed in a carrier is critical to maintain proper deposition uniformity. This spacing is determined by slots in the quartz carriers or "boats". The slots are typically formed by support rods. If these slots are too large, which is possible because of manufacturing error or because of excessive wear, carried wafers can acquire an undesired "tilt". Such a tilt can change the spacing between wafers, making the deposition nonuniform. This tilt is called "teepeeing" by those skilled in the art.
Needless to say, it is important to be able to determine the amount of wafer tilt to ensure that it falls within an acceptable range. Heretofore, those skilled in the art have mechanically measured slot width with plug gauges, calipers, and the like, and have used the measurements obtained by such means to estimate any associated tilt. A shortcoming of this approach is the fact that tilt is measured indirectly and, therefore, an error factor arises. Another shortcoming of this approach is the fact that it involves contact with the boat itself, and therefore ultimately causes boat wear. Yet another shortcoming of this approach is the fact that teepeeing arising due to sagging of the underlying supports (another common source of tilt) is not accurately detected by slot width measurement. Those skilled in the art have also devised other techniques for attempting to determine wafer tilt. Some, like laser imaging, are too expensive to be practical; others employ organics that ultimately damage boats being evaluated. In short, heretofore there has been a strong need in the art for a wafer tilt gauge that is inexpensive, accurate, and non-damaging to boats.